1. Field of the Invention
The present invention relates to a wiring substrate and a method of fabricating the same.
2. Description of the Related Art
With portable electronic appliances such as mobile phones, PDAs, DVCs and DSCs becoming more and more advanced in their capabilities, miniaturization and weight reduction of products have become essential for market acceptance. Accordingly, highly-integrated system LSIs for achieving these goals are demanded. Also, better ease and convenience of use are required of these electronic appliances. In this respect, high capabilities and high performance are required of LSIs used in these appliances. While the number of I/Os is increasing as a result of increasingly high integration of LSI chips, there is also a persistent requirement for miniaturization of packages themselves. In order to meet these incompatible demands, development of a semiconductor package adapted for high-density substrate mounting of semiconductor components is in serious demand. A packaging technology called chip size packaging (CSP) has been developed in a variety of forms to address these requirements. For example, the patent document No. 1 discloses a CSP technology.
In such a semiconductor package, vias are provided in an insulating resin film for electric connection with circuit elements. In the related art, a via is formed by first forming a via hole in an insulating resin film, forming a thin film in the via hole by electroless plating or the like, and subsequently filling the via hole by electroplating.
Recently, with an increase in the operating speed of electronic appliances, copper has come to be used as a material for forming a via or wiring. One problem with forming a copper via in two stages as described above is that adhesion between the film formed by electroless plating and the film formed by electroplating is poor. Another problem is that stress migration or electromigration occurs at an interface between the films, making the wiring less reliable.
Relate Art List
    Patent Document No. 1    Japanese Patent Application Laid-Open No. 2003-249498    Patent Document No. 2    Japanese Patent Application Laid-Open No. 2002-110717